LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY test_adder IS
   PORT(
       clk,reset	:	IN STD_LOGIC;
       test_pass,result_active	:	OUT STD_LOGIC;
       part_clock	:	OUT STD_LOGIC
       );
END test_adder;

ARCHITECTURE structure OF test_adder IS

COMPONENT testbench IS
   PORT(
       clk,reset	:	IN STD_LOGIC;
       part_out		: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
       test_pass,result_active	:	OUT STD_LOGIC;
       part_in1, part_in2	:	OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
       part_clock	:	OUT STD_LOGIC
       );
END COMPONENT;

COMPONENT adder_32bit IS
	PORT
	(
		dataa		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		datab		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
	);
END COMPONENT;

SIGNAL dataa,datab,result	:	STD_LOGIC_VECTOR(31 DOWNTO 0);

BEGIN

bench: testbench port map(clk,reset,result,test_pass,result_active,dataa,datab,part_clock);
adder: adder_32bit port map(dataa,datab,result);

END structure;       
